diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-03-10 21:09:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:08:02 +0000 |
| commit | 77298c6820a0f4424a41d9f740f379f88f51e406 (patch) | |
| tree | 8b98460562808c3e205583f435b71af744bf618d /src/soc/intel/alderlake/espi.c | |
| parent | 8bd525001fa7d051965ffd2bad2e7e5ecd0dd547 (diff) | |
soc/intel/alderlake: add processor power limits control support
Add processor power limits control support to configure values for
alderlake soc based platforms.
BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board
Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/espi.c')
0 files changed, 0 insertions, 0 deletions