diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-08-11 21:33:53 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-08-19 13:52:38 +0000 |
| commit | c0c477741d0089fb1eb83e4c88b6ad5ba1661cb9 (patch) | |
| tree | b876ceb22cec6744c161d2ec23d82ef3e3f5719a /src/soc/intel/alderlake/chipset.cb | |
| parent | 191a8d7d2e40b9c90d81cf8e5ea3fad414afeb29 (diff) | |
soc/intel/alderlake: set default PL4 values for different SKUs
Set default PL4 values for various Alder Lake CPU SKUs as per
bug#191906315 comment#10.
BUG=b:194745919
BRANCH=None
TEST=Build FW and test on brya0 board.
Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 2d5c54e4ae..05da658eac 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -5,21 +5,25 @@ chip soc/intel/alderlake register "power_limits_config[ADL_P_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, + .tdp_pl4 = 123, }" register "power_limits_config[ADL_P_POWER_LIMITS_482_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, + .tdp_pl4 = 140, }" register "power_limits_config[ADL_P_POWER_LIMITS_682_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, + .tdp_pl4 = 215, }" register "power_limits_config[ADL_M_POWER_LIMITS_282_CORE]" = "{ .tdp_pl1_override = 9, .tdp_pl2_override = 30, + .tdp_pl4 = 68, }" device domain 0 on |