diff options
| author | Curtis Chen <curtis.chen@intel.com> | 2021-12-21 11:51:33 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-10 14:26:16 +0000 |
| commit | 150fee60cc6f30fe3dddcf504958cd2b916f469b (patch) | |
| tree | 7f1a227f32489e795ff6d975b7c9e61beebca136 /src/soc/intel/alderlake/chipset.cb | |
| parent | 502a761221ed14c4b381fe33350c9f9d17ec0d76 (diff) | |
soc/intel/alderlake: Update the ADL-P SKU parameters for VR domains
We support all the ADL-P 15W/28W/45W SKU's and map them with the
latest VR configurations. These config values are generated by iPDG
application with ADL-P platform package tool.
RDC Kit ID for the iPDG tools
* Intel(R) Platform Design Studio Installer: 610905
* Intel(R) Platform Design Studio - Libraries: 613643
* Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345
* Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ida7a6df0422a9a3972646cb3bdd0112b5efa2755
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 24 |
1 files changed, 9 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 60c149a72d..c956fd4826 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -2,13 +2,13 @@ chip soc/intel/alderlake device cpu_cluster 0 on end - register "power_limits_config[ADL_P_282_CORE]" = "{ + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ .tdp_pl1_override = 15, .tdp_pl2_override = 55, .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_482_CORE]" = "{ + register "power_limits_config[ADL_P_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 90, @@ -20,7 +20,13 @@ chip soc/intel/alderlake .tdp_pl4 = 140, }" - register "power_limits_config[ADL_P_682_45W_CORE]" = "{ + register "power_limits_config[ADL_P_442_482_45W_CORE]" = "{ + .tdp_pl1_override = 45, + .tdp_pl2_override = 95, + .tdp_pl4 = 125, + }" + + register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{ .tdp_pl1_override = 45, .tdp_pl2_override = 115, .tdp_pl4 = 215, @@ -42,18 +48,6 @@ chip soc/intel/alderlake .tdp_pl4 = 68, }" - register "power_limits_config[ADL_P_242_CORE]" = "{ - .tdp_pl1_override = 15, - .tdp_pl2_override = 55, - .tdp_pl4 = 123, - }" - - register "power_limits_config[ADL_P_442_45W_CORE]" = "{ - .tdp_pl1_override = 45, - .tdp_pl2_override = 95, - .tdp_pl4 = 125, - }" - # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |