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authorSugnan Prabhu S <sugnan.prabhu.s@intel.com>2021-03-18 22:08:22 +0530
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-04-22 15:59:25 +0000
commit50f8b4ebdd7db8077b87ab7686637599c9d93af3 (patch)
treee0ba2ff31243e54108ee8c0a44c27d7abf59447e /src/soc/intel/alderlake/chip.h
parentc1c1ba5582fa0302476491c46f18cc73b69c88ac (diff)
soc/intel/alderlake: Add enum for HDA audio configuration
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
-rw-r--r--src/soc/intel/alderlake/chip.h19
1 files changed, 16 insertions, 3 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index e0d0b6074f..201150e8fc 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -113,9 +113,22 @@ struct soc_intel_alderlake_config {
/* Audio related */
uint8_t PchHdaDspEnable;
- uint8_t PchHdaIDispLinkTmode;
- uint8_t PchHdaIDispLinkFrequency;
- uint8_t PchHdaIDispCodecDisconnect;
+
+ /* iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T */
+ enum {
+ HDA_TMODE_2T = 0,
+ HDA_TMODE_4T = 2,
+ HDA_TMODE_8T = 3,
+ HDA_TMODE_16T = 4,
+ } PchHdaIDispLinkTmode;
+
+ /* iDisp-Link Freq 4: 96MHz, 3: 48MHz. */
+ enum {
+ HDA_LINKFREQ_48MHZ = 3,
+ HDA_LINKFREQ_96MHZ = 4,
+ } PchHdaIDispLinkFrequency;
+
+ bool PchHdaIDispCodecEnable;
struct pcie_rp_config pch_pcie_rp[CONFIG_MAX_PCH_ROOT_PORTS];
struct pcie_rp_config cpu_pcie_rp[CONFIG_MAX_CPU_ROOT_PORTS];