diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2021-10-06 13:02:34 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-03 15:48:27 +0000 |
| commit | fc69b9d5efd2df202d6fe21f1e2c1abda1e6dbfa (patch) | |
| tree | 5eae5ac21430d6ec61f0439af5922fe139ac046a /src/soc/intel/alderlake/chip.h | |
| parent | 2a30359d5a8717825f7e7fb43e1feffa951b275c (diff) | |
soc/intel/alderlake: Add the CnviDdrRfim configuration
FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim
config to control the CnviDdrRfim UPD from devicetree. Setting
CnviDdrRfim to 1 enable CNVi DDR RFIM
BUG=b:201724512
BRANCH=None
TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value.
Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index afabcf088e..771fc5aaa7 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -554,6 +554,11 @@ struct soc_intel_alderlake_config { * 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16; see enum slew_rate for values */ uint8_t SlowSlewRate[NUM_VR_DOMAINS]; + + /* CNVi DDR RFIM Enable/Disable + * Default 0. Setting this to 1 enable CNVi DDR RFIM. + */ + bool CnviDdrRfim; }; typedef struct soc_intel_alderlake_config config_t; |