diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-05-07 20:11:53 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-07 19:02:02 +0000 |
| commit | aa49608a2bf474355f0a7cf767e10326259254ed (patch) | |
| tree | cf105fd3ea9503085c6b32042a214a1ad21c1981 /src/soc/intel/alderlake/chip.h | |
| parent | 29405483cedca2035d1d0229a2ec893e53a6dcc9 (diff) | |
soc/intel/adl: Add SKU specific power limits support
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 57b78688ee..853de1cccb 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -17,13 +17,22 @@ #include <soc/usb.h> #include <stdint.h> +/* Types of different SKUs */ +enum soc_intel_alderlake_power_limits { + ADL_P_POWER_LIMITS_282_CORE, + ADL_P_POWER_LIMITS_482_CORE, + ADL_P_POWER_LIMITS_682_CORE, + ADL_M_POWER_LIMITS_282_CORE, + ADL_POWER_LIMITS_COUNT +}; + struct soc_intel_alderlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[ADL_POWER_LIMITS_COUNT]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ |