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authorMarx Wang <marx.wang@intel.corp-partner.google.com>2022-12-20 10:48:33 +0800
committerMartin L Roth <gaumless@gmail.com>2022-12-22 18:47:50 +0000
commit39ede0af15f17bf853d7b3208d301dc623251c29 (patch)
tree3a407ce5120cd1570f5a8e6da9dbc6b070fe0917 /src/soc/intel/alderlake/chip.h
parent174d2635fd3fda2f3bd3c33ebafce2f4a4561663 (diff)
soc/intel/alderlake: Add Raptor Lake device IDs
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
-rw-r--r--src/soc/intel/alderlake/chip.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a732fe6e8a..82493a7eba 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -136,6 +136,7 @@ static const struct {
{ PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W },
{ PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W },
{ PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W },
+ { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W },
};
/* Types of display ports */