diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-12-31 11:43:29 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-18 07:28:51 +0000 |
| commit | f8248f38a10c6dc664b043445233c8f69c3af0f6 (patch) | |
| tree | a2d700007dc43c09fa8878f21750eb39065e3140 /src/soc/intel/alderlake/chip.c | |
| parent | de2ab41fc43152b652af7c1f658b1c27926afd6c (diff) | |
soc/intel/alderlake: Update PCH and CPU PCIe RP table
According ADL EDS to update the PCH and CPU PCIe RP table.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chip.c')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 95b6b8f307..c7e3fb8c2f 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -14,15 +14,10 @@ #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/pci_devs.h> +#include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> -static const struct pcie_rp_group pch_lp_rp_groups[] = { - { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, - { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, - { 0 } -}; - #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) { @@ -150,7 +145,7 @@ void soc_init_pre_device(void *chip_info) soc_fill_gpio_pm_configuration(); /* Swap enabled PCI ports in device tree if needed. */ - pcie_rp_update_devicetree(pch_lp_rp_groups); + pcie_rp_update_devicetree(get_pch_pcie_rp_table()); } static struct device_operations pci_domain_ops = { |