diff options
| author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-04-15 18:15:44 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-28 09:19:09 +0000 |
| commit | 933a44b80d3b414282fe0c7b060cb7fd0dc6cf90 (patch) | |
| tree | b200142f7b76c295fa1054b4e58932f1a8deca79 /src/soc/intel/alderlake/chip.c | |
| parent | f422ed898dfaaadf69409c1a79ffb5157f8897d6 (diff) | |
soc/alderlake: Add ADL-S PCIe support
Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/chip.c')
| -rw-r--r-- | src/soc/intel/alderlake/chip.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 96ff354b9e..21b59a187f 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -73,9 +73,15 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + case SA_DEVFN_CPU_PCIE1_0: return "PEG1"; + case SA_DEVFN_CPU_PCIE1_1: return "PEG2"; + case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; +#else case SA_DEVFN_CPU_PCIE1_0: return "PEG2"; case SA_DEVFN_CPU_PCIE6_0: return "PEG0"; case SA_DEVFN_CPU_PCIE6_2: return "PEG1"; +#endif case SA_DEVFN_IGD: return "GFX0"; case SA_DEVFN_TCSS_XHCI: return "TXHC"; case SA_DEVFN_TCSS_XDCI: return "TXDC"; @@ -110,6 +116,25 @@ const char *soc_acpi_name(const struct device *dev) case PCH_DEVFN_PCIE10: return "RP10"; case PCH_DEVFN_PCIE11: return "RP11"; case PCH_DEVFN_PCIE12: return "RP12"; + case PCH_DEVFN_PCIE13: return "RP13"; + case PCH_DEVFN_PCIE14: return "RP14"; + case PCH_DEVFN_PCIE15: return "RP15"; + case PCH_DEVFN_PCIE16: return "RP16"; + case PCH_DEVFN_PCIE17: return "RP17"; + case PCH_DEVFN_PCIE18: return "RP18"; + case PCH_DEVFN_PCIE19: return "RP19"; + case PCH_DEVFN_PCIE20: return "RP20"; + case PCH_DEVFN_PCIE21: return "RP21"; + case PCH_DEVFN_PCIE22: return "RP22"; + case PCH_DEVFN_PCIE23: return "RP23"; + case PCH_DEVFN_PCIE24: return "RP24"; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) + /* Avoid conflicts with PCH-N eMMC */ + case PCH_DEVFN_PCIE25: return "RP25"; + case PCH_DEVFN_PCIE26: return "RP26"; + case PCH_DEVFN_PCIE27: return "RP27"; + case PCH_DEVFN_PCIE28: return "RP28"; +#endif case PCH_DEVFN_PMC: return "PMC"; case PCH_DEVFN_UART0: return "UAR0"; case PCH_DEVFN_UART1: return "UAR1"; |