diff options
| author | zhixingma <zhixing.ma@intel.com> | 2022-06-13 15:06:27 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-28 21:01:27 +0000 |
| commit | 529a64b788888aa21189104309a5e9e814bcb0e0 (patch) | |
| tree | 4d296c1b555fed9bc70dd9f884c79e14c7aa31ce /src/soc/intel/alderlake/bootblock | |
| parent | dd582b0cb10932fae8198c928172af49deeab34e (diff) | |
soc/intel: Add Raptor Lake device IDs
Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.
References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/bootblock')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/report_platform.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index f069d9862c..6d6261b13a 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -35,6 +35,7 @@ static struct { { CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" }, { CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" }, { CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" }, + { CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" }, }; static struct { @@ -72,6 +73,8 @@ static struct { { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" }, { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, + { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, + }; static struct { @@ -196,6 +199,9 @@ static struct { { PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" }, { PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" }, { PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" }, + { PCI_DID_INTEL_RPL_P_GT4, "Raptorlake P GT4" }, + { PCI_DID_INTEL_RPL_P_GT5, "Raptorlake P GT5" }, + { PCI_DID_INTEL_RPL_P_GT6, "Raptorlake P GT6" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) |