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| author | Selma Bensaid <selma.bensaid@intel.com> | 2021-09-21 15:57:51 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-30 13:37:00 +0000 |
| commit | 4df35b6ec88be35a946565438a4c5c51fc3ad3b9 (patch) | |
| tree | 78735de3c0349b3a9c9684e618b7a90c37aeeec2 /src/soc/intel/alderlake/bootblock | |
| parent | 03aef28f1613809c788b513d28873ac23bcca341 (diff) | |
mb/intel/adlrvp_m: correct SSD power sequence
This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/bootblock')
0 files changed, 0 insertions, 0 deletions