diff options
| author | Reka Norman <rekanorman@chromium.org> | 2023-09-22 15:26:54 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-10-04 15:29:32 +0000 |
| commit | a5215c4eb3a4cbe0ef32257c4da2e5a6e0febdef (patch) | |
| tree | f41a03dd91791e30e8483a2623d010af9b590fe9 /src/soc/intel/alderlake/acpi | |
| parent | 773d4b8fb00613b373d81e877a7014c338542e86 (diff) | |
soc/intel: Move USB wake methods to a common ASL file
The ACPI methods for enabling USB wake are identical on ADL, CNL and
SKL. Move them to a common ASL file so they can be reused more easily
on other SoCs.
Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks
in devicetree to a common header.
BUG=b:300844110
TEST=Use abuild to build kinox, puff, and fizz with and without this
change. Check the generated dsdt.aml is unchanged.
Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/xhci.asl | 47 |
1 files changed, 2 insertions, 45 deletions
diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index e4001fe8c2..1c3bbbe2da 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include <intelblocks/xhci.h> #include <soc/gpe.h> -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 &= PORTSCN_BITS_OFF_MASK - Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 &= (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include <soc/intel/common/acpi/xhci_wake.asl> /* XHCI Controller 0:14.0 */ |