diff options
| author | Sean Rhodes <sean@starlabs.systems> | 2022-05-21 10:38:09 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-09 13:48:54 +0000 |
| commit | 0a162919197f832abab13df54032f9e4e003da70 (patch) | |
| tree | f0bb86fed9b991891f5681dd7931c88f99ed7035 /src/soc/intel/alderlake/acpi | |
| parent | 843f34e32a7c4e5da7ee2ef2cf402d52a8a1f4fc (diff) | |
soc/intel/alderlake: Add config option for S3 ACPI
Add Kconfig option `SOC_INTEL_ALDERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.
This patch is the Alder Lake equivalent of CB:59024.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I04df8e106f9d53337b9eb5d2b9041b44a0e36684
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss.asl | 8 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_dma.asl | 22 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_pcierp.asl | 20 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/acpi/tcss_xhci.asl | 6 |
4 files changed, 55 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index c8cea84dd8..66aa908709 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -41,6 +41,12 @@ Scope (\_SB) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) + Name (S0IX, 0) +#else + Name (S0IX, 1) +#endif + /* Device base address */ Method (BASE, 1) { @@ -573,6 +579,7 @@ Scope (\_SB.PCI0) } } +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -643,6 +650,7 @@ Scope (\_SB.PCI0) STAT = 0 } } +#endif /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 0b5e03f913..989fbd5c96 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,25 +28,45 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { - Return (0x4) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) + Return (0x04) +#else + Return (0x03) +#endif } Method (_PR0) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } Method (_PR3) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If (DUID == 0) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If (DUID == 0) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 799c0ce94f..dee265c3a3 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -267,25 +267,45 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) +#else + Return (0x3) +#endif } Method (_PR0) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } Method (_PR3) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) If ((TUID == 0) || (TUID == 1)) { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) } Else { Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) } +#else + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.TBT1 }) + } +#endif } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index acbeb30c13..b3fe653d26 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,7 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Return (0x4) +#else + Return (0x3) +#endif } /* @@ -39,6 +43,7 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) +#if !CONFIG(SOC_INTEL_ALDERLAKE_S3) Method (_PR0) { Return (Package () { \_SB.PCI0.D3C }) @@ -48,6 +53,7 @@ Method (_PR3) { Return (Package () { \_SB.PCI0.D3C }) } +#endif /* * XHCI controller _DSM method |