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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-05-18 09:04:42 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-06-29 21:54:00 +0000
commit43607e4751d41e57d16f31a8a882a331e5493be1 (patch)
tree9824e8d362e4f63b93fccc14dfad6ee49cbc9395 /src/soc/intel/alderlake/acpi
parentf9bb1b46a27511e7f2b49d9ab9c1f56335afc1b3 (diff)
soc/intel/alderlake: Enable support for common IRQ block
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
-rw-r--r--src/soc/intel/alderlake/acpi/pci_irqs.asl147
-rw-r--r--src/soc/intel/alderlake/acpi/southbridge.asl3
2 files changed, 0 insertions, 150 deletions
diff --git a/src/soc/intel/alderlake/acpi/pci_irqs.asl b/src/soc/intel/alderlake/acpi/pci_irqs.asl
deleted file mode 100644
index 3fdd0775ed..0000000000
--- a/src/soc/intel/alderlake/acpi/pci_irqs.asl
+++ /dev/null
@@ -1,147 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-#include <soc/irq.h>
-
-Name (PICP, Package () {
- /* D31: HDA, SMBus, TraceHub, GbE */
- Package(){0x001FFFFF, 0, 0, TRACEHUB_IRQ },
- /* D30: UART0, UART1, SPI0, SPI1 */
- Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
- Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
- Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
- Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
- /* D29: RP9 ~ RP12 */
- Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
- Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
- Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
- Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
- /* D28: RP1 ~ RP8 */
- Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, /* RP 1 and 5 */
- Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, /* RP 2 and 6 */
- Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, /* RP 3 and 7 */
- Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, /* RP 4 and 8 */
- /* D25: I2C4, I2C5, UART2 */
- Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
- Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
- Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
- /* D23: SATA */
- Package(){0x0017FFFF, 0, 0, SATA_IRQ },
- /* D22: CSME */
- Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
- Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
- Package(){0x0016FFFF, 2, 0, CSME_IDE_IRQ },
- Package(){0x0016FFFF, 3, 0, CSME_KT_IRQ },
- /* D21: I2C0 ~ I2C3 */
- Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
- Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
- Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
- Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
- /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
- Package(){0x0014FFFF, 0, 0, xHCI_IRQ },
- Package(){0x0014FFFF, 1, 0, xDCI_IRQ },
- /* D18: ISH, SPI2 */
- Package(){0x0012FFFF, 0, 0, ISH_IRQ },
- Package(){0x0012FFFF, 1, 0, LPSS_SPI2_IRQ },
- /* D17: UART3 */
- Package(){0x0011FFFF, 0, 0, LPSS_UART3_IRQ },
- /* D16: THC0, THC1 */
- Package(){0x0010FFFF, 0, 0, THC0_IRQ },
- Package(){0x0010FFFF, 1, 0, THC1_IRQ },
- /* D13: xHCI, xDCI */
- Package(){0x000DFFFF, 0, 0, CPU_xHCI_IRQ },
- Package(){0x000DFFFF, 1, 0, CPU_xDCI_IRQ },
- /* D8: GNA */
- Package(){0x0008FFFF, 0, 0, GNA_IRQ },
- /* D7: TBT PCIe */
- Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ },
- Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ },
- Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ },
- Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ },
- /* D6: PEG60 */
- Package(){0x0006FFFF, 0, 0, PEG_IRQ },
- /* D5: IPU Device */
- Package(){0x0005FFFF, 0, 0, IPU_IRQ },
- /* D4: Thermal Device */
- Package(){0x0004FFFF, 0, 0, THERMAL_IRQ },
- /* D2: IGFX */
- Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
-})
-
-Name (PICN, Package () {
- /* D31: HDA, SMBUS, TRACEHUB */
- Package(){0x001FFFFF, 0, 0, 11 },
- Package(){0x001FFFFF, 1, 0, 10 },
- Package(){0x001FFFFF, 2, 0, 11 },
- Package(){0x001FFFFF, 3, 0, 11 },
- /* D30: UART0, UART1, SPI0, SPI1 */
- Package(){0x001EFFFF, 0, 0, 11 },
- Package(){0x001EFFFF, 1, 0, 10 },
- Package(){0x001EFFFF, 2, 0, 11 },
- Package(){0x001EFFFF, 3, 0, 11 },
- /* D29: RP9 ~ RP12 */
- Package(){0x001DFFFF, 0, 0, 11 },
- Package(){0x001DFFFF, 1, 0, 10 },
- Package(){0x001DFFFF, 2, 0, 11 },
- Package(){0x001DFFFF, 3, 0, 11 },
- /* D28: RP1 ~ RP8 */
- Package(){0x001CFFFF, 0, 0, 11 },
- Package(){0x001CFFFF, 1, 0, 10 },
- Package(){0x001CFFFF, 2, 0, 11 },
- Package(){0x001CFFFF, 3, 0, 11 },
- /* D25: I2C4, I2C5, UART2 */
- Package(){0x0019FFFF, 0, 0, 11 },
- Package(){0x0019FFFF, 1, 0, 10 },
- Package(){0x0019FFFF, 2, 0, 11 },
- /* D23: SATA */
- Package(){0x0017FFFF, 0, 0, 11 },
- /* D22: CSME */
- Package(){0x0016FFFF, 0, 0, 11 },
- Package(){0x0016FFFF, 1, 0, 10 },
- Package(){0x0016FFFF, 2, 0, 11 },
- Package(){0x0016FFFF, 3, 0, 11 },
- /* D21: I2C0 ~ I2C3 */
- Package(){0x0015FFFF, 0, 0, 11 },
- Package(){0x0015FFFF, 1, 0, 10 },
- Package(){0x0015FFFF, 2, 0, 11 },
- Package(){0x0015FFFF, 3, 0, 11 },
- /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */
- Package(){0x0014FFFF, 0, 0, 11 },
- Package(){0x0014FFFF, 1, 0, 10 },
- Package(){0x0014FFFF, 2, 0, 11 },
- /* D19: SPI3 */
- Package(){0x0013FFFF, 0, 0, 11 },
- /* D18: ISH, SPI2 */
- Package(){0x0012FFFF, 0, 0, 11 },
- Package(){0x0012FFFF, 1, 0, 10 },
- /* D17: UART3 */
- Package(){0x0011FFFF, 0, 0, 11 },
- /* D16: THC0, THC1 */
- Package(){0x0010FFFF, 0, 0, 11 },
- Package(){0x0010FFFF, 1, 0, 10 },
- /* D13: xHCI, xDCI */
- Package(){0x000DFFFF, 0, 0, 11 },
- Package(){0x000DFFFF, 1, 0, 10 },
- /* D8: GNA */
- Package(){0x0008FFFF, 0, 0, 11 },
- /* D7: TBT PCIe */
- Package(){0x0007FFFF, 0, 0, 11 },
- Package(){0x0007FFFF, 1, 0, 10 },
- Package(){0x0007FFFF, 2, 0, 11 },
- Package(){0x0007FFFF, 3, 0, 11 },
- /* D6: PEG60 */
- Package(){0x0006FFFF, 0, 0, 11 },
- /* D5: IPU Device */
- Package(){0x0005FFFF, 0, 0, 11 },
- /* D4: Thermal Device */
- Package(){0x0004FFFF, 0, 0, 11 },
- /* D2: IGFX */
- Package(){0x0002FFFF, 0, 0, 11 },
-})
-
-Method (_PRT)
-{
- If (PICM) {
- Return (^PICP)
- } Else {
- Return (^PICN)
- }
-}
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl
index 3a53f2c9d1..59bcf7461f 100644
--- a/src/soc/intel/alderlake/acpi/southbridge.asl
+++ b/src/soc/intel/alderlake/acpi/southbridge.asl
@@ -5,9 +5,6 @@
#include <soc/itss.h>
#include <soc/pcr_ids.h>
-/* PCI IRQ assignment */
-#include "pci_irqs.asl"
-
/* PCR access */
#include <soc/intel/common/acpi/pcr.asl>