diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-03-23 14:48:53 +0530 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-26 19:44:15 +0000 |
| commit | 36ca7b3104301db721097ab1e4aebb4a6958725c (patch) | |
| tree | 296a8ba64fc2efed731fbe4a20a80bc45cb7e77a /src/soc/intel/alderlake/acpi | |
| parent | 532e8c059e3209530ebf56545df3f1f7a82c6ccf (diff) | |
soc/intel: Move USB PORTSC definition into IA common code
This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.
TEST=Able to build and boot google/taeko where USB wake is working.
Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi')
| -rw-r--r-- | src/soc/intel/alderlake/acpi/xhci.asl | 18 |
1 files changed, 3 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index 465f0aa0b1..e4001fe8c2 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -1,18 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <intelblocks/xhci.h> #include <soc/gpe.h> -#define PORTSCN_OFFSET 0x480 -#define PORTSCXUSB3_OFFSET 0x540 - -#define WAKE_ON_CONNECT_DISCONNECT_ENABLE 0x6000000 -/* - * And port status/control reg with RO and RWS bits - * RO bits: 0, 2:3, 10:13, 24, 28:30 - * RWS bits: 5:9, 14:16, 25:27 - */ -#define RO_BITS_OFF_MASK ~0x80FE0012 - /* * USB Port Wake Enable (UPWE) on usb attach/detach * Arg0 - Port Number @@ -30,10 +20,8 @@ Method (UPWE, 3, Serialized) PSCT, 32, } Local0 = PSCT - - Local0 &= RO_BITS_OFF_MASK - /* Set WCE and WDE bits */ - Local0 |= WAKE_ON_CONNECT_DISCONNECT_ENABLE + Local0 &= PORTSCN_BITS_OFF_MASK + Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE PSCT = Local0 } |