diff options
author | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 13:02:06 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-06 12:29:58 +0000 |
commit | 080899244192922fac12c97d1f81854c38851636 (patch) | |
tree | 7f8fce9affd2e910ae25ba7691abba5a80659fdb /src/soc/intel/alderlake/acpi/southbridge.asl | |
parent | 1fa35859fe6af0ddea205136c96234dc04b89cba (diff) |
soc/intel/alderlake/acpi: Add SoC ACPI directory for ADL
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi/southbridge.asl')
-rw-r--r-- | src/soc/intel/alderlake/acpi/southbridge.asl | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl new file mode 100644 index 0000000000..373dca5840 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/itss.h> +#include <intelblocks/pcr.h> +#include <soc/itss.h> +#include <soc/pcr_ids.h> + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" + +/* PCR access */ +#include <soc/intel/common/acpi/pcr.asl> + +/* PCH clock */ +#include "camera_clock_ctl.asl" + +/* GPIO controller */ +#include "gpio.asl" + +/* ESPI 0:1f.0 */ +#include <soc/intel/common/block/acpi/acpi/lpc.asl> + +/* PCH HDA */ +#include "pch_hda.asl" + +/* PCIE Ports */ +#include "pcie.asl" + +/* Serial IO */ +#include "serialio.asl" + +/* SMBus 0:1f.4 */ +#include <soc/intel/common/block/acpi/acpi/smbus.asl> + +/* ISH 0:12.0 */ +#include <soc/intel/common/block/acpi/acpi/ish.asl> + +/* USB XHCI 0:14.0 */ +#include "xhci.asl" + +/* PCI _OSC */ +#include <soc/intel/common/acpi/pci_osc.asl> + +/* PMC Core*/ +#include <soc/intel/common/block/acpi/acpi/pmc.asl> + +/* GbE 0:1f.6 */ +#include <soc/intel/common/block/acpi/acpi/pch_glan.asl> |