diff options
author | Subrata Banik <subrata.banik@intel.com> | 2020-10-03 13:02:06 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-06 12:29:58 +0000 |
commit | 080899244192922fac12c97d1f81854c38851636 (patch) | |
tree | 7f8fce9affd2e910ae25ba7691abba5a80659fdb /src/soc/intel/alderlake/acpi/camera_clock_ctl.asl | |
parent | 1fa35859fe6af0ddea205136c96234dc04b89cba (diff) |
soc/intel/alderlake/acpi: Add SoC ACPI directory for ADL
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
Change-Id: I7509e8c46038b1edfc501db74e763f198efb56ab
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/acpi/camera_clock_ctl.asl')
-rw-r--r-- | src/soc/intel/alderlake/acpi/camera_clock_ctl.asl | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl b/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl new file mode 100644 index 0000000000..3c65058c64 --- /dev/null +++ b/src/soc/intel/alderlake/acpi/camera_clock_ctl.asl @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x1 +#define B_ICLK_PCR_REQUEST 0x2 + +/* The clock control registers for each IMGCLK are offset by 0xC */ +#define B_ICLK_PCR_OFFSET 0xC + +Scope (\_SB.PCI0) { + + /* IsCLK PCH base register for clock settings */ + Name (ICKB, 0) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 + /* + * Helper function for Read And Or Write + * Arg0 : Clock source select + * Arg1 : And data + * Arg2 : Or data + */ + Method (RAOW, 3, Serialized) + { + OperationRegion (ICLK, SystemMemory, (ICKB + (Arg0 * B_ICLK_PCR_OFFSET)), 4) + Field (ICLK, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Local0 = VAL0 + VAL0 = Local0 & Arg1 | Arg2 + } + + /* + * Clock control Method + * Arg0: Clock source select (0 .. 5 => IMGCLKOUT_0 .. IMGCLKOUT_5) + * Arg1: Frequency select (0: 24MHz, 1: 19.2MHz) + */ + Method (MCON, 0x2, NotSerialized) + { + /* Set Clock Frequency */ + RAOW (Arg0, ~B_ICLK_PCR_FREQUENCY, Arg1) + + /* Enable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, B_ICLK_PCR_REQUEST) + } + + Method (MCOF, 0x1, NotSerialized) + { + /* Disable Clock */ + RAOW (Arg0, ~B_ICLK_PCR_REQUEST, 0) + } +} |