diff options
| author | Zhixing Ma <zhixing.ma@intel.com> | 2022-09-27 11:11:58 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-14 15:58:33 +0000 |
| commit | eb3532768198c71b39c28c36769b04d2b8176bca (patch) | |
| tree | 71b888159d9c590e56a62a15041046007c0a1a16 /src/soc/intel/alderlake/Makefile.inc | |
| parent | e109a6a47f2c1e3fc6ad162645d3654d190ea455 (diff) | |
soc/intel/alderlake: Fix unknown max speed in SMBIOS
The current SMBIOS for coreboot is missing processor info for Alder Lake
and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements max speed function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS max speed value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I09bcccc6f97238f7328224af8b852751114896fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/alderlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/alderlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index b400837961..e9266c0da4 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += tcss.c ramstage-y += vr_config.c ramstage-y += xhci.c ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +ramstage-y += smbios.c smm-y += elog.c smm-y += p2sb.c |