diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-21 19:35:40 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-09-22 06:37:14 +0000 |
| commit | c38d92789901002faf6cd1c64c689d29ab269e2e (patch) | |
| tree | ad21d07e8c3c36e9c7df740d1d9067496464b338 /src/soc/intel/alderlake/Kconfig | |
| parent | 4ca7b26346db521f9530e5a4affe4202dc837e6e (diff) | |
soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM Kconfig
Earlier generation platform used `HeciEnabled` chip config (set to 0)
and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at
the end of the post. `HeciEnabled` chip config remains enabled in all
latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig
selection from SoC Kconfig as CSE remains default enabled.
BUG=b:200644229
TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device
is listed with `lspci`.
Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b87861b281..b135bbe95b 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -86,7 +86,6 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select UDK_202005_BINDING select DISPLAY_FSP_VERSION_INFO - select HECI_DISABLE_USING_SMM config ALDERLAKE_CAR_ENHANCED_NEM bool |