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authorMichał Żygowski <michal.zygowski@3mdeb.com>2022-04-08 17:02:35 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-06-16 00:01:20 +0000
commit9df95d99dc8c26b4f70e497a7cfc47782f273c61 (patch)
tree00716cced58184ecf884aeb424aad157f04b7247 /src/soc/intel/alderlake/Kconfig
parentbda2a15113c1f76ac2d2cb1ebd79b0aea6f20204 (diff)
soc/intel/alderlake: Unselect USB4 and TCSS options for ADL-S
Alder Lake-S CPUs do not have TCSS and USB4 devices. Unselect them. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ifc643d440107754dfe1a0844964f70de670cb1f1 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
-rw-r--r--src/soc/intel/alderlake/Kconfig13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 0357ba9e2d..86366bfa2d 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -105,11 +105,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
- select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
- select SOC_INTEL_COMMON_BLOCK_USB4
- select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
- select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BASECODE
@@ -126,6 +122,15 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select UDK_202005_BINDING
+config SOC_INTEL_ALDERLAKE_TCSS_USB4_SUPPORT
+ bool
+ default y if !SOC_INTEL_ALDERLAKE_PCH_S
+ default n if SOC_INTEL_ALDERLAKE_PCH_S
+ select SOC_INTEL_COMMON_BLOCK_TCSS
+ select SOC_INTEL_COMMON_BLOCK_USB4
+ select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
+ select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
+
config ALDERLAKE_CONFIGURE_DESCRIPTOR
bool
help