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| author | Michał Kopeć <michal.kopec@3mdeb.com> | 2022-04-08 11:28:45 +0200 |
|---|---|---|
| committer | Michał Żygowski <michal.zygowski@3mdeb.com> | 2022-06-30 13:54:48 +0000 |
| commit | 75a49fe856830d97baf882caf35962577d7cba5e (patch) | |
| tree | 958e0b196872d728bcae2d973c9ebe34dc5bbe81 /src/soc/intel/alderlake/Kconfig | |
| parent | a08f509cc537e3608a41930592a6cb9ea81df6ab (diff) | |
soc/intel/alderlake: add chipset devicetree for ADL-S
Add chipset devicetree and power limits for AlderLake-S platform.
Based on Intel docs #619501, #619362 and #626343.
Change-Id: I1dd72465c458b718ecfcb29c2f7e433a63b89807
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 25f456b6ac..d14b9a9c48 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -177,6 +177,7 @@ config FSP_TEMP_RAM_SIZE config CHIPSET_DEVICETREE string + default "soc/intel/alderlake/chipset_pch_s.cb" if SOC_INTEL_ALDERLAKE_PCH_S default "soc/intel/alderlake/chipset.cb" config EXT_BIOS_WIN_BASE |