diff options
author | Vadim Bendebury <vbendeb@chromium.org> | 2014-09-02 13:20:47 -0700 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-23 15:34:18 +0100 |
commit | c7b3f727f5ce95fdee26ef819263e9efb70e7a54 (patch) | |
tree | 1fe386448cd8415c60cbfe90feff19c9107108c8 /src/soc/imgtec | |
parent | a252a759c8bac6a5f42af74ddca2139724f6018f (diff) |
danube: use SOC specific rom stage code
Romstage initialization code does not need to be board specific, keep
it in the SOC directory. Should there be a need for the board specific
code, it can be added later.
BUG=chrome-os-partner:31438
TEST=with upcoming patches, the urara board coreboot builds fine
Change-Id: Ib619fa9313d463ded13e9259e50bb5aeaab4fb05
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c08977aaa5e9b5da29359d1920d7d8b61ce86d3
Original-Change-Id: I27e2d225bd36c42ccd29128d0ea9a970566c02af
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/215992
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/imgtec')
-rw-r--r-- | src/soc/imgtec/danube/Makefile.inc | 1 | ||||
-rw-r--r-- | src/soc/imgtec/danube/romstage.c | 39 |
2 files changed, 40 insertions, 0 deletions
diff --git a/src/soc/imgtec/danube/Makefile.inc b/src/soc/imgtec/danube/Makefile.inc index d7628ede51..6a2ba4f3d4 100644 --- a/src/soc/imgtec/danube/Makefile.inc +++ b/src/soc/imgtec/danube/Makefile.inc @@ -36,6 +36,7 @@ ramstage-y += cbmem.c ramstage-y += timestamp.c romstage-y += cbmem.c +romstage-y += romstage.c romstage-y += timestamp.c # Generate the actual coreboot bootblock code diff --git a/src/soc/imgtec/danube/romstage.c b/src/soc/imgtec/danube/romstage.c new file mode 100644 index 0000000000..53ca898fed --- /dev/null +++ b/src/soc/imgtec/danube/romstage.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Imagination Technologies + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/hlt.h> +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + console_init(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + CONFIG_CBFS_PREFIX "/ramstage"); + if (entry != (void *)-1) + stage_exit(entry); + + hlt(); +} |