diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-05-15 16:54:17 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-05-26 22:09:34 +0200 |
| commit | def0fb57dfd91e6599c622a7b2769164a5c02ef0 (patch) | |
| tree | eb4da4e71b5a21a2864bcac895a462554543383e /src/soc/imgtec | |
| parent | 807127f8cc5ca63951c48e78ad1bcf2bd2c7dc22 (diff) | |
pistashio: bump up romstage size
Making large changes in pieces is leading to a little bloat.
Bump up the romstage size temporarily so that jenkins will be
happy.
Change-Id: I6f9facb4ca488cf41741a3ed6d0ed7f66d4778b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10220
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/imgtec')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/memlayout.ld | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index 326a26bb79..b36d47e9b6 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -38,8 +38,8 @@ SECTIONS * and then through the identity mapping in ROM stage. */ SRAM_START(0x1a000000) - ROMSTAGE(0x1a005000, 36K) - PRERAM_CBFS_CACHE(0x1a00e000, 72K) + ROMSTAGE(0x1a005000, 40K) + PRERAM_CBFS_CACHE(0x1a00f000, 68K) SRAM_END(0x1a020000) /* Bootblock executes out of KSEG0 and sets up the identity mapping. |