New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>

4 files changed, 41 insertions, 33 deletions

diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
index 2e8b700007..70e5741cf1 100644
--- a/src/soc/imgtec/pistachio/Kconfig
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -35,10 +35,6 @@ config BOOTBLOCK_CPU_INIT
 	string
 	default "soc/imgtec/pistachio/bootblock.c"
 
-config BOOTBLOCK_BASE
-	hex
-	default 0x9b000000
-
 config CBFS_ROM_OFFSET
 	hex
 	default 0x4100
@@ -48,31 +44,4 @@ config CBFS_HEADER_ROM_OFFSET
 	hex
 	default 0x4000
 
-config ROMSTAGE_BASE
-	hex
-	default 0x9b004000
-	help
-	  The address where romstage is supposed to be loaded, right above the
-	  bootblock.
-
-config CBMEM_CONSOLE_PRERAM_BASE
-        hex "memory address of the CBMEM console buffer"
-        default 0x9b00f800
-	help
-	  Allocate 4KB to the pre-ram console buffer, we should be able to use
-	  GRAM eventually and have a much larger buffer.
-
-config BOOTBLOCK_STACK_BOTTOM
-	hex
-	default 0x9b00e000
-	help
-	  This allocates 6KB of stack space. One needs to verify that this is
-	  sufficient.
-
-config BOOTBLOCK_STACK_TOP
-	hex
-	default CBMEM_CONSOLE_PRERAM_BASE
-	help
-	  Bootblock stack starts immediately under the CBMEM console buffer,
-	  stack location might be changed by romstage.
 endif
diff --git a/src/soc/imgtec/pistachio/Makefile.inc b/src/soc/imgtec/pistachio/Makefile.inc
index b91bb1b59a..d052c8f435 100644
--- a/src/soc/imgtec/pistachio/Makefile.inc
+++ b/src/soc/imgtec/pistachio/Makefile.inc
@@ -51,5 +51,5 @@ $(objcbfs)/bootblock.raw: $(objcbfs)/bootblock.elf
 # Create a complete bootblock which will start up the system
 $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw $(BIMGTOOL)
 	@printf "    BIMGTOOL   $(subst $(obj)/,,$(@))\n"
-	$(BIMGTOOL) $< $@ $(CONFIG_BOOTBLOCK_BASE)
+	$(BIMGTOOL) $< $@ $(call loadaddr,bootblock)
 
diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c
index 5fb6c0e7bd..373d4f853d 100644
--- a/src/soc/imgtec/pistachio/cbmem.c
+++ b/src/soc/imgtec/pistachio/cbmem.c
@@ -21,9 +21,10 @@
 
 #include <cbmem.h>
 #include <stdlib.h>
+#include <symbols.h>
 
 void *cbmem_top(void)
 {
 	uintptr_t top = MIN(CONFIG_DRAM_SIZE_MB, 256) << 20;
-	return (void *)(top + CONFIG_SYS_SDRAM_BASE);
+	return _dram + top;
 }
diff --git a/src/soc/imgtec/pistachio/memlayout.ld b/src/soc/imgtec/pistachio/memlayout.ld
new file mode 100644
index 0000000000..21c3d73d5f
--- /dev/null
+++ b/src/soc/imgtec/pistachio/memlayout.ld
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <memlayout.h>
+
+#include <arch/header.ld>
+
+/* TODO: This should be revised by someone who understands the SoC better. */
+
+SECTIONS
+{
+	CBFS_CACHE(0x0, 0) /* TODO: fix this, it was already broken before!!! */
+
+	DRAM_START(0x80000000)
+	RAMSTAGE(0x80000000, 128K)
+
+	/* TODO: Does this SoC use SRAM? Add SRAM_START() and SRAM_END(). */
+	BOOTBLOCK(0x9B000000, 16K)
+	ROMSTAGE(0x9B004000, 40K)
+	STACK(0x9B00E000, 6K)
+	PRERAM_CBMEM_CONSOLE(0x9B00F800, 3K)
+}