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authorPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-11-10 00:35:02 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2019-03-07 12:47:01 +0000
commitc9b7d1fb57787d7037a5bce031a1300d13f5df40 (patch)
tree57788b70b069229693dae5727cb8acc54eee3c14 /src/soc/imgtec/pistachio
parent7a732b4781e7b83abda3230055d7110e1db730f3 (diff)
security/tpm: Fix TCPA log feature
Until now the TCPA log wasn't working correctly. * Refactor TCPA log code. * Add TCPA log dump fucntion. * Make TCPA log available in bootblock. * Fix TCPA log formatting. * Add x86 and Cavium memory for early log. Change-Id: Ic93133531b84318f48940d34bded48cbae739c44 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/soc/imgtec/pistachio')
-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index 05042efb9f..cd81093fab 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -46,7 +46,8 @@ SECTIONS
REGION(gram_bootblock, 0x1a000000, 28K, 1)
ROMSTAGE(0x1a007000, 60K)
VBOOT2_WORK(0x1a016000, 12K)
- PRERAM_CBFS_CACHE(0x1a019000, 48K)
+ VBOOT2_TPM_LOG(0x1a019000, 2K)
+ PRERAM_CBFS_CACHE(0x1a019800, 46K)
SRAM_END(0x1a066000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.