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authorJulius Werner <jwerner@chromium.org>2019-10-30 16:12:24 -0700
committerPatrick Georgi <pgeorgi@google.com>2019-11-20 10:10:44 +0000
commit63c444a69b98bc8a86719699423b3273cc5759e8 (patch)
tree6bd90603b343103bdcd730eb5f9aca6c4500fb6f /src/soc/imgtec/pistachio/reset.c
parent5027ecfb1987cf06efc772a0bee0a1fe1dc38049 (diff)
Remove imgtec/pistachio SoC
After removing urara no board still uses this SoC, and there are no plans to add any in the future (I'm not sure if the chip really exists tbh...). Change-Id: Ic4628fdfacc9fb19b6210394d96431fdb5f8e8f1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36491 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/reset.c')
-rw-r--r--src/soc/imgtec/pistachio/reset.c26
1 files changed, 0 insertions, 26 deletions
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
deleted file mode 100644
index cc563372b4..0000000000
--- a/src/soc/imgtec/pistachio/reset.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <reset.h>
-
-#define PISTACHIO_WD_ADDR 0xB8102100
-#define PISTACHIO_WD_SW_RST_OFFSET 0x0000
-
-void do_board_reset(void)
-{
- /* Generate system reset */
- write32_x(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);
-}