diff options
| author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-01-26 13:15:12 +0000 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-14 12:08:23 +0200 |
| commit | 8b1f23ef0307974737f49b237664f66f5e2c35c7 (patch) | |
| tree | 29e27ae1b988b3f331bf0966a32c053b87fa5308 /src/soc/imgtec/pistachio/include | |
| parent | 125427a07f7eec03d924f8cb3378bbe954804319 (diff) | |
urara: add clock setup for MIPS CPU, ROM and Ethernet
BUG=chrome-os-partner:31438
TEST=tested on Pistachio bring up board; works properly
BRANCH=none
Change-Id: Ie386d6af9eeba7a72b1b88d515e6cb1821569c6b
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: d4b8d8b6f965296f9ecf62da8e5f383c3667b077
Original-Change-Id: I9eb464340b0475ae735ba5573ab0841dac0d74eb
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/243215
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9669
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/imgtec/pistachio/include')
| -rw-r--r-- | src/soc/imgtec/pistachio/include/soc/clocks.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h index 95b35857a5..f57d43d89e 100644 --- a/src/soc/imgtec/pistachio/include/soc/clocks.h +++ b/src/soc/imgtec/pistachio/include/soc/clocks.h @@ -22,13 +22,15 @@ /* Functions for PLL setting */ int sys_pll_setup(u8 divider1, u8 divider2); -int mips_pll_setup(u8 divider1, u8 divider2i, u8 predivider, u32 feedback); +int mips_pll_setup(u8 divider1, u8 divider2, u8 predivider, u32 feedback); /* Peripheral divider setting */ -void uart1_clk_setup(u8 divider1, u16 divider2); void system_clk_setup(u8 divider); +void mips_clk_setup(u8 divider1, u8 divider2); +void uart1_clk_setup(u8 divider1, u16 divider2); int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel); - +void rom_clk_setup(u8 divider); +void eth_clk_setup(u8 mux, u8 divider); enum { CLOCKS_OK = 0, PLL_TIMEOUT = -1, |