urara: Configure clocks and MFIOs

Set elements:
	- UART1 clock dividers and MFIOs
	- SPIM1 clock dividers and MFIOs
	- USB clock dividers
	- System clock divider
	- System PLL
	- MIPS CPU PLL

BUG=chrome-os-partner:31438
TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB
have proper functionality.
BRANCH=none

Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151
Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/241423
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/9662
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 39 insertions, 0 deletions

diff --git a/src/soc/imgtec/pistachio/include/soc/clocks.h b/src/soc/imgtec/pistachio/include/soc/clocks.h
new file mode 100644
index 0000000000..95b35857a5
--- /dev/null
+++ b/src/soc/imgtec/pistachio/include/soc/clocks.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Imagination Technologies
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
+#define __SOC_IMGTEC_PISTACHIO_CLOCKS_H__
+
+#include <stdint.h>
+
+/* Functions for PLL setting */
+int sys_pll_setup(u8 divider1, u8 divider2);
+int mips_pll_setup(u8 divider1, u8 divider2i, u8 predivider, u32 feedback);
+
+/* Peripheral divider setting */
+void uart1_clk_setup(u8 divider1, u16 divider2);
+void system_clk_setup(u8 divider);
+int usb_clk_setup(u8 divider, u8 refclksel, u8 fsel);
+
+enum {
+	CLOCKS_OK = 0,
+	PLL_TIMEOUT = -1,
+	USB_TIMEOUT = -2,
+	USB_VBUS_FAULT = -3
+};
+
+#endif