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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-11-02 16:55:44 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-11-08 19:23:49 +0000 |
| commit | 2d69d75749b7c320fec9c50403add0cea3272687 (patch) | |
| tree | f13fdc9a2c104a8511de736b554394efbab18eab /src/soc/imgtec/pistachio/cbmem.c | |
| parent | b838256a51b3d58f297165b5d238ea35aba3bce7 (diff) | |
amd/stoneyridge: Add northbridge register macros
Add helpers for determining the D18F1 offset for MMIO base and limit,
and I/O base/limit registers.
Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/cbmem.c')
0 files changed, 0 insertions, 0 deletions