soc/intel/pantherlake: Update power limits config

This updates power_limits_config for Panther Lake U and H.

Source:
  Intel PTL PDG 813278
  Intel PTL FSP Power limit profiles table

BUG=b:357011633
TEST=Build fatcat and boot with Panther Lake SoC and RVP.

Change-Id: I1b9276af7f1e30b1cda3d8c016524fd6397fa4b2
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

0 files changed, 0 insertions, 0 deletions