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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-09-13 22:18:56 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-14 20:41:10 +0000 |
| commit | badea79500b46f00f07308af17b55b5adfd0ce81 (patch) | |
| tree | 8df4f456eca1f28f9409b35fe275b75a6f884b4a /src/soc/example | |
| parent | e74da16741623521bb08ffb74e8d54729a24d3a9 (diff) | |
mb/amd/gardenia: deselect HAVE_PIRQ_TABLE and drop incorrect irq_tables
This file isn't correct, since the Stoneyridge SoC doesn't have a legacy
PCI bridge on bus 0 bridge 0x14 function 4. Google/Kahlee doesn't select
HAVE_PIRQ_TABLE, so it's likely safe to also not select it for this
board.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf470b9ff7823019772d43af98ebc47af395728
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/example')
0 files changed, 0 insertions, 0 deletions