x86: Add a minimal example SoC along with a board

The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.

This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.

As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.

Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 76 insertions, 0 deletions

diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig
new file mode 100644
index 0000000000..38b23c0dd2
--- /dev/null
+++ b/src/soc/example/min86/Kconfig
@@ -0,0 +1,25 @@
+config SOC_EXAMPLE_MIN86
+	bool
+	help
+	  This example SoC code along with the example/min86 mainboard
+	  should serve as a minimal example how a buildable x86 SoC code
+	  base can look like.
+
+	  This can serve, for instance, as a basis to add new SoCs to
+	  coreboot. Starting with a buildable commit should help with
+	  the review of the actual code, and also avoid any regressions
+	  when common coreboot code changes.
+
+if SOC_EXAMPLE_MIN86
+
+config SOC_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_ALL_STAGES_X86_32
+	select NO_MONOTONIC_TIMER
+	select NO_MMCONF_SUPPORT
+	select UNKNOWN_TSC_RATE
+
+config DCACHE_BSP_STACK_SIZE		# required by arch/x86/car.ld
+	default 0x100
+
+endif
diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc
new file mode 100644
index 0000000000..9c1c7f0331
--- /dev/null
+++ b/src/soc/example/min86/Makefile.inc
@@ -0,0 +1,15 @@
+ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y)
+
+bootblock-y	+= cache_as_ram.S
+bootblock-y	+= ../../../cpu/intel/car/bootblock.c
+
+postcar-y	+= exit_car.S
+
+romstage-y	+= romstage.c
+
+ramstage-y	+= chip.c
+ramstage-y	+= timer.c
+
+subdirs-y	+= ../../../cpu/x86/mtrr
+
+endif
diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S
new file mode 100644
index 0000000000..a350143834
--- /dev/null
+++ b/src/soc/example/min86/cache_as_ram.S
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global bootblock_pre_c_entry
+
+.code32
+bootblock_pre_c_entry:
+	call	bootblock_c_entry_bist
+
+.Lhlt:
+	hlt
+	jmp	.Lhlt
diff --git a/src/soc/example/min86/chip.c b/src/soc/example/min86/chip.c
new file mode 100644
index 0000000000..dd09891e3c
--- /dev/null
+++ b/src/soc/example/min86/chip.c
@@ -0,0 +1,3 @@
+#include <device/device.h>
+
+struct chip_operations soc_example_min86_ops = { NULL };
diff --git a/src/soc/example/min86/exit_car.S b/src/soc/example/min86/exit_car.S
new file mode 100644
index 0000000000..0f1b227c2d
--- /dev/null
+++ b/src/soc/example/min86/exit_car.S
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global chipset_teardown_car
+
+.code32
+chipset_teardown_car:
+	/* Return to caller. */
+	jmp	*%esp
diff --git a/src/soc/example/min86/romstage.c b/src/soc/example/min86/romstage.c
new file mode 100644
index 0000000000..91074b2012
--- /dev/null
+++ b/src/soc/example/min86/romstage.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+
+asmlinkage void car_stage_entry(void)
+{
+}
diff --git a/src/soc/example/min86/timer.c b/src/soc/example/min86/timer.c
new file mode 100644
index 0000000000..9054ffd972
--- /dev/null
+++ b/src/soc/example/min86/timer.c
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <delay.h>
+
+void init_timer(void)
+{
+}