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| author | Raul E Rangel <rrangel@chromium.org> | 2021-05-05 13:38:27 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-06 23:31:26 +0000 |
| commit | 8317e727ce5d97626d7f59ac515d208502830ad1 (patch) | |
| tree | 97afdaf3f2a87e0894ad39b4e306b5d9a9885914 /src/soc/example/min86/chip.c | |
| parent | 6eced03b25954e370e20e62f2cbe41f9d5626eae (diff) | |
soc/amd/common/espi,mb/: Allow configuring open drain ALERT#
Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/example/min86/chip.c')
0 files changed, 0 insertions, 0 deletions