x86: Add a minimal example SoC along with a board

The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.

This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.

As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.

Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 11 insertions, 0 deletions

diff --git a/src/soc/example/min86/cache_as_ram.S b/src/soc/example/min86/cache_as_ram.S
new file mode 100644
index 0000000000..a350143834
--- /dev/null
+++ b/src/soc/example/min86/cache_as_ram.S
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+.global bootblock_pre_c_entry
+
+.code32
+bootblock_pre_c_entry:
+	call	bootblock_c_entry_bist
+
+.Lhlt:
+	hlt
+	jmp	.Lhlt