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author | Nico Huber <nico.h@gmx.de> | 2020-09-24 23:33:34 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2020-10-30 21:34:18 +0000 |
commit | 1fa72d5fe1d2ac41036c08355c760fb576899347 (patch) | |
tree | e6e135c24eae9b0a58417dc5e5099f72545f5488 /src/soc/example/min86/Makefile.inc | |
parent | 8661fe220d92cedbb5eb7956d74b764670d354f3 (diff) |
x86: Add a minimal example SoC along with a board
The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.
This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.
As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.
Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/example/min86/Makefile.inc')
-rw-r--r-- | src/soc/example/min86/Makefile.inc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/example/min86/Makefile.inc b/src/soc/example/min86/Makefile.inc new file mode 100644 index 0000000000..9c1c7f0331 --- /dev/null +++ b/src/soc/example/min86/Makefile.inc @@ -0,0 +1,15 @@ +ifeq ($(CONFIG_SOC_EXAMPLE_MIN86),y) + +bootblock-y += cache_as_ram.S +bootblock-y += ../../../cpu/intel/car/bootblock.c + +postcar-y += exit_car.S + +romstage-y += romstage.c + +ramstage-y += chip.c +ramstage-y += timer.c + +subdirs-y += ../../../cpu/x86/mtrr + +endif |