x86: Add a minimal example SoC along with a board

The min86 example SoC code along with the example mainboard
should serve as a minimal example how a buildable x86 SoC code
base can look like.

This can serve, for instance, as a basis to add new SoCs to
coreboot. Starting with a buildable commit should help with
the review of the actual code, and also avoid any regressions
when common coreboot code changes.

As the example code itself is build-tested, it should advance
with coreboot and can't rot like documentation might. It also
serves as a check what APIs need to be implemented with the
default Kconfig settings.

Change-Id: Id76ab15fe77ae3e405c43f9c8677694f178be112
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45710
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 25 insertions, 0 deletions

diff --git a/src/soc/example/min86/Kconfig b/src/soc/example/min86/Kconfig
new file mode 100644
index 0000000000..38b23c0dd2
--- /dev/null
+++ b/src/soc/example/min86/Kconfig
@@ -0,0 +1,25 @@
+config SOC_EXAMPLE_MIN86
+	bool
+	help
+	  This example SoC code along with the example/min86 mainboard
+	  should serve as a minimal example how a buildable x86 SoC code
+	  base can look like.
+
+	  This can serve, for instance, as a basis to add new SoCs to
+	  coreboot. Starting with a buildable commit should help with
+	  the review of the actual code, and also avoid any regressions
+	  when common coreboot code changes.
+
+if SOC_EXAMPLE_MIN86
+
+config SOC_SPECIFIC_OPTIONS
+	def_bool y
+	select ARCH_ALL_STAGES_X86_32
+	select NO_MONOTONIC_TIMER
+	select NO_MMCONF_SUPPORT
+	select UNKNOWN_TSC_RATE
+
+config DCACHE_BSP_STACK_SIZE		# required by arch/x86/car.ld
+	default 0x100
+
+endif