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authorJohn Zhao <john.zhao@intel.com>2019-04-22 10:45:51 -0700
committerNico Huber <nico.h@gmx.de>2019-05-11 11:16:48 +0000
commit1159a163cd36318d27f8f3b71617ad4a5b781efb (patch)
tree05f00bfd909ae3fb52669596e9e5f23ab096bf8b /src/soc/cavium
parent4249348735d18cb2d44506090a675a29b0567e7f (diff)
soc/intel/cnl: Enable VT-d
Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Diffstat (limited to 'src/soc/cavium')
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