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| author | Matt DeVillier <matt.devillier@gmail.com> | 2020-10-07 13:27:55 -0500 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:36:31 +0000 |
| commit | 30f583264d0e9154804cbcdfd8c65518f5e3560f (patch) | |
| tree | c2e9c2101cbd6e85fae8cd5b2695a4e28de386de /src/soc/cavium | |
| parent | 89d5c2b6e431bb1f41c8a525b50ffa4ac03d156e (diff) | |
mb/google/jecht: Disable PCIe AER
Ethernet hardware on jecht variants doesn't support AER, so
disable it to mitigate continuous AER timeout errors in dmesg:
> pcieport 0000:00:1c.0: AER: Corrected error received: 0000:00:1c.0
> pcieport 0000:00:1c.0: AER: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID)
> pcieport 0000:00:1c.0: AER: device [8086:9c94] error status/mask=00001000/00002000
> pcieport 0000:00:1c.0: AER: [12] Timeout
Change-Id: Ieda82c6e13c2bbc4b3a051a3d2a7ae90728ccdc6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46137
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium')
0 files changed, 0 insertions, 0 deletions