diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2021-10-05 14:11:13 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-13 17:38:57 +0000 |
| commit | 5705b63a08d28ddf8c5a22600e19aa8dd8513614 (patch) | |
| tree | e5ffe8b2dd6259a55064abec5449acdade01113f /src/soc/cavium | |
| parent | 2d17ea4d501c8e0f68813cda80dd6412b10ca0d8 (diff) | |
soc/amd/common: Add support to read and set SPI speeds from verstage
Currently all SPI speed configurations are done through EFS at build
time. There is a need to apply SPI speed overrides at run-time - eg.
based on board version after assessing the signal integrity. This
override configuration can be carried out by PSP verstage and bootblock.
Export the APIs to set and read SPI speeds from both PSP verstage and
bootblock.
BUG=None
TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I281531e506b56173471b918c746f58d1ad97162c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/cavium')
0 files changed, 0 insertions, 0 deletions