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author | Subrata Banik <subrata.banik@intel.com> | 2020-01-21 14:28:26 +0530 |
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committer | Subrata Banik <subrata.banik@intel.com> | 2020-01-23 05:06:12 +0000 |
commit | f8d9a13aba3b7a82934914bce3b820c428ff98f3 (patch) | |
tree | 3c1d3650a6d2e9d9a8f4e9b8c6eec2598e4fb839 /src/soc/cavium | |
parent | 6476e415124731c9082d92263f4e99645a6f1424 (diff) |
soc/intel/common: Update SA bit fields as per EDS
This patch updates system agent related registers bit definitions
as per EDS.
For example:
As per CNL/ICL EDS MCHBAR register base is between bit 16-38
but coreboot programming was not aligned with EDS previously.
CNL EDS doc number: 566216
Also provide provision to program 64bit values as per SA EDS definitions
TEST=Dump MCHBAR in coreboot and ASL shows same 32 bit value.
Change-Id: I37340408fe89c94ce81953c751c8d7e22bc81a42
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/cavium')
0 files changed, 0 insertions, 0 deletions