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| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-29 18:19:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:19:03 +0000 |
| commit | 759448893c508cd61240b4598336ecdc7f36eba6 (patch) | |
| tree | 0ed8d37d25744466786fa57c7fc22edb5c7c59d8 /src/soc/cavium/common | |
| parent | e29dcdcdd8bc04e9c54aca4e341d0b8168763000 (diff) | |
soc/nvidia/tegra210: Fix flushing SPI fifo
This will avoid clearing the other bits in fifo_status.
Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/cavium/common')
0 files changed, 0 insertions, 0 deletions