cavium: Add CN81xx SoC and eval board support

This adds Cavium CN81xx SoC and SFF EVB files.

Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK

BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs

romstage:
- Use minimal DRAM init only

devicetree:
- Convert FTD to static C file containing key value pairs

Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)

Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init

Not working:
- Booting a payload
- Booting upstream ATF

TODO:
- Configuration straps

Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c
new file mode 100644
index 0000000000..c61a8d7dc1
--- /dev/null
+++ b/src/soc/cavium/common/bootblock.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present  Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <console/console.h>
+#include <delay.h>
+#include <program_loading.h>
+#include <symbols.h>
+#include <timestamp.h>
+#include <soc/bootblock.h>
+
+DECLARE_OPTIONAL_REGION(timestamp);
+
+__attribute__((weak)) void bootblock_mainboard_early_init(void) { /* no-op */ }
+__attribute__((weak)) void bootblock_soc_early_init(void) { /* do nothing */ }
+__attribute__((weak)) void bootblock_soc_init(void) { /* do nothing */ }
+__attribute__((weak)) void bootblock_mainboard_init(void) { /* do nothing */ }
+
+
+/* C code entry point for the boot block */
+void bootblock_main(const uint64_t reg_x0,
+		    const uint64_t reg_x1,
+		    const uint64_t reg_pc)
+{
+	uint64_t base_timestamp = 0;
+
+	init_timer();
+
+	if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS))
+		base_timestamp = timestamp_get();
+
+	/* Initialize timestamps if we have TIMESTAMP region in memlayout.ld. */
+	if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0)
+		timestamp_init(base_timestamp);
+
+	bootblock_soc_early_init();
+	bootblock_mainboard_early_init();
+
+	if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
+		console_init();
+		exception_init();
+
+		if (reg_x0)
+			printk(BIOS_ERR,
+			       "BOOTBLOCK: RST Boot Failure Code %lld\n",
+			       reg_x0);
+
+		printk(BIOS_DEBUG, "BOOTBLOCK: FDT 0x%llX\n", reg_x1);
+	}
+
+	bootblock_soc_init();
+	bootblock_mainboard_init();
+
+	run_romstage();
+}