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| author | Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> | 2023-06-02 13:06:06 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-06-21 13:31:34 +0000 |
| commit | 4eee50642ff5ac6e7d7830afd38693943fe17b5b (patch) | |
| tree | 8468375914af28a58212828682c8125b88abed16 /src/soc/cavium/cn81xx/uart.c | |
| parent | 3ea0202925a9535ca58184cfad736122c97e4d41 (diff) | |
mb/google/rex/var/screebo: set HBR smbus pin as NC
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case it prevents ese and cse from entering suspend.
BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.
Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/uart.c')
0 files changed, 0 insertions, 0 deletions