diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-11 11:59:07 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-13 06:49:23 +0000 |
| commit | 46514c2b877c29c2d7c2061a9785736e270c0c62 (patch) | |
| tree | 2f78550192bce548139ef49fdac6623dad578703 /src/soc/cavium/cn81xx/include | |
| parent | 00148bba7146318e2e815d8c13e33278f63814c9 (diff) | |
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/cavium/cn81xx/include')
| -rw-r--r-- | src/soc/cavium/cn81xx/include/soc/memlayout.ld | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld deleted file mode 100644 index 79673c9974..0000000000 --- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <soc/addressmap.h> -#include <arch/header.ld> - -SECTIONS -{ - DRAM_START(0x00000000) - /* Secure region 0 - 1MiB */ - BL31(0, 0xe0000) - REGION(sff8104, 0xe0000, 0x20000, 0x1000) - - /* Insecure region 1MiB - TOP OF DRAM */ - /* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */ - SRAM_START(BOOTROM_OFFSET) - - STACK(BOOTROM_OFFSET, 16K) - TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K) - PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K) - FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K) - PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K) - BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K) - VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K) - TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K) - VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K) - ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K) - - SRAM_END(BOOTROM_OFFSET + 0x80000) - - TTB(BOOTROM_OFFSET + 0x80000, 512K) - RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K) - /* Stack for secondary CPUs */ - REGION(stack_sec, BOOTROM_OFFSET + 0x180000, - CONFIG_MAX_CPUS * CONFIG_STACK_SIZE, 0x1000) - - /* Leave some space for the payload */ - POSTRAM_CBFS_CACHE(0x2000000, 16M) -} |