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| author | Huayang Duan <huayang.duan@mediatek.com> | 2020-06-23 16:26:26 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-12-31 03:08:13 +0000 |
| commit | 9e685b764ac6ab41e6c7cb5f7cd3d147506d9dc6 (patch) | |
| tree | cf7c07a6ad8e64f78b0585d866fbf2d29560dca0 /src/soc/cavium/cn81xx/ecam0.c | |
| parent | c43e9899662fa6342f38a3ca42a2e2b4282e4484 (diff) | |
soc/mediatek/mt8192: Add DDR mode register init
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: If200f4dcef0b1d0b7e901d4ae6e667b1f75156f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/ecam0.c')
0 files changed, 0 insertions, 0 deletions