aboutsummaryrefslogtreecommitdiff
path: root/src/soc/cavium/cn81xx/chip.h
diff options
context:
space:
mode:
authorDavid Hendricks <dhendricks@fb.com>2017-12-01 20:49:48 -0800
committerPatrick Rudolph <siro@das-labor.org>2018-07-10 07:01:57 +0000
commit8cbd569f74d8929387730e45b0d6e993b1365c02 (patch)
treeca6414a4d81e37280887b0da0f1a6120a50f0a3a /src/soc/cavium/cn81xx/chip.h
parent03d31427338ba59d3a354ac1beb3b0c153471768 (diff)
cavium: Add CN81xx SoC and eval board support
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/soc/cavium/cn81xx/chip.h')
-rw-r--r--src/soc/cavium/cn81xx/chip.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/cavium/cn81xx/chip.h b/src/soc/cavium/cn81xx/chip.h
new file mode 100644
index 0000000000..9716a5da6a
--- /dev/null
+++ b/src/soc/cavium/cn81xx/chip.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018-present Facebook, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_CAVIUM_CN81XX_CHIP_H
+#define __SOC_CAVIUM_CN81XX_CHIP_H
+
+struct soc_cavium_cn81xx_config {
+};
+
+#endif /* __SOC_CAVIUM_CN81XX_CHIP_H */