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authorMartin Roth <martinroth@google.com>2017-06-24 21:34:58 -0600
committerMartin Roth <martinroth@google.com>2017-07-16 19:22:25 +0000
commit99aa6ce053f5122a98713b8353de6b8a72182cad (patch)
treec181ba483922dadf346c153415884d3f25c4ee22 /src/soc/broadcom
parent7a1a3ad2ce3403f0379b72d30360e2bed02e9c26 (diff)
src/soc: add IS_ENABLED() around Kconfig symbol references
Change-Id: I2e7b756296e861e08cea846297f687a880daaf45 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/broadcom')
-rw-r--r--src/soc/broadcom/cygnus/ddr_init.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
index 5c4c985366..1a5fd86bb0 100644
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ b/src/soc/broadcom/cygnus/ddr_init.c
@@ -475,7 +475,7 @@ int is_ddr_32bit(void)
{
int ddr32 = 0;
-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)
+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)
ddr32=1;
#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */
@@ -966,7 +966,7 @@ static int try_restore_shmoo(void)
reg = (uint32_t *)(*flptr++);
val = (uint32_t *)(*flptr++);
if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))
+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
|| (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
#endif
#ifdef CONFIG_IPROC_DDR_ECC
@@ -1068,7 +1068,7 @@ void iproc_save_shmoo_values(void)
*ptr++ = val;
chksum += val;
}
-#if (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS))
+#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
if (is_ddr_32bit()) {
for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
@@ -1479,7 +1479,7 @@ void ddr_init2(void)
}
}
-#if CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
+#if IS_ENABLED(CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE)
#if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff)
/* Enable auto self-refresh */
reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,