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authorElyes HAOUAS <ehaouas@noos.fr>2018-08-09 18:55:58 +0200
committerMartin Roth <martinroth@google.com>2018-08-10 21:25:53 +0000
commit3d45000c9cab2e5e5cac11a0a6af9abdce8aa80d (patch)
tree7b5096ca1f81fecf70418020aba184e446f995e0 /src/soc/broadcom/cygnus/include
parent1895838e7a3807a6fce324f0dfed193a3821f6df (diff)
src: Fix typo
Change-Id: I689c5663ef59861f79b68220abd146144f7618de Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/broadcom/cygnus/include')
-rw-r--r--src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
index 93489bb8d4..7e233fa2d4 100644
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
+++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
@@ -38,7 +38,7 @@
#endif /* GET & SET */
/***************************************************************************
- *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Comand control registers
+ *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers
***************************************************************************/
#define DDR34_CORE_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */
#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 /* PHY PLL status register */