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authorRaul E Rangel <rrangel@chromium.org>2021-03-16 20:29:06 -0600
committerFelix Held <felix-coreboot@felixheld.de>2021-05-09 18:10:29 +0000
commitf486fcc9985f57c87e2a44a0cc7f1fdc8af32740 (patch)
treeb9e046e1ac0cfd03002e8291211e81db61c5a102 /src/soc/amd
parentfd7ed87746d763feff7d26dba9598b505e8750c1 (diff)
soc/amd/cezanne: Generate PCI routing table
Use the new acpigen_write_PRT to write the _PRT for each PCI bridge. BUG=b:184766519 TEST=Dump guybrush ACPI table and verify it looks correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/acpi/soc.asl2
-rw-r--r--src/soc/amd/cezanne/pcie_gpp.c30
2 files changed, 30 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl
index 5039ca1faf..e603307c2f 100644
--- a/src/soc/amd/cezanne/acpi/soc.asl
+++ b/src/soc/amd/cezanne/acpi/soc.asl
@@ -12,6 +12,8 @@ Scope(\_SB) {
#include "pci_int_defs.asl"
+ #include <soc/amd/common/acpi/pci_int.asl>
+
#include "mmio.asl"
#include "pci0.asl"
diff --git a/src/soc/amd/cezanne/pcie_gpp.c b/src/soc/amd/cezanne/pcie_gpp.c
index 4ab206b231..16c6b23243 100644
--- a/src/soc/amd/cezanne/pcie_gpp.c
+++ b/src/soc/amd/cezanne/pcie_gpp.c
@@ -1,6 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi_device.h>
+#include <acpi/acpigen.h>
+#include <acpi/acpigen_pci.h>
+#include <amdblocks/amd_pci_util.h>
+#include <assert.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -46,6 +50,28 @@ static const char *pcie_gpp_acpi_name(const struct device *dev)
}
}
+static void acpi_device_write_gpp_pci_dev(const struct device *dev)
+{
+ const char *scope = acpi_device_scope(dev);
+ const char *name = acpi_device_name(dev);
+
+ assert(dev->path.type == DEVICE_PATH_PCI);
+ assert(name);
+ assert(scope);
+
+ acpigen_write_scope(scope);
+ acpigen_write_device(name);
+
+ acpigen_write_ADR_pci_device(dev);
+ acpigen_write_STA(acpi_device_status(dev));
+
+ /* b/187083211 - Enable GNB IO-APIC */
+ acpigen_write_pci_FCH_PRT(dev);
+
+ acpigen_pop_len(); /* Device */
+ acpigen_pop_len(); /* Scope */
+}
+
static struct device_operations internal_pcie_gpp_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
@@ -53,7 +79,7 @@ static struct device_operations internal_pcie_gpp_ops = {
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.acpi_name = pcie_gpp_acpi_name,
- .acpi_fill_ssdt = acpi_device_write_pci_dev,
+ .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
};
static const struct pci_driver internal_pcie_gpp_driver __pci_driver = {
@@ -69,7 +95,7 @@ static struct device_operations external_pcie_gpp_ops = {
.scan_bus = pciexp_scan_bridge,
.reset_bus = pci_bus_reset,
.acpi_name = pcie_gpp_acpi_name,
- .acpi_fill_ssdt = acpi_device_write_pci_dev,
+ .acpi_fill_ssdt = acpi_device_write_gpp_pci_dev,
};
static const unsigned short external_pci_gpp_ids[] = {