diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-12-22 13:05:12 -0700 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-01-15 02:24:08 +0000 |
| commit | e5f627ab853128be8db6778a22c2926f3ff3b188 (patch) | |
| tree | b19f8f9d8991cbca6d2ffaab40b2a3699bf806a0 /src/soc/amd | |
| parent | 8420ccc6e96de717581409c64eb740563bf7c9f3 (diff) | |
soc/amd/common/psp_verstage: Report HSP Secure State
Get Hardware Security Processor(HSP) state in PSP Verstage through the
SVC call and report it in cbmem logs.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS in Skyrim.
Change-Id: Ic4875d1732f22783a90434329188192b106168f4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/psp_verstage/include/psp_verstage.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/psp_verstage.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/psp_verstage/chipset.c | 16 |
3 files changed, 21 insertions, 0 deletions
diff --git a/src/soc/amd/common/psp_verstage/include/psp_verstage.h b/src/soc/amd/common/psp_verstage/include/psp_verstage.h index e740332862..dd3d2b35ca 100644 --- a/src/soc/amd/common/psp_verstage/include/psp_verstage.h +++ b/src/soc/amd/common/psp_verstage/include/psp_verstage.h @@ -68,4 +68,6 @@ void platform_report_mode(int developer_mode_enabled); void update_psp_fw_hash_table(const char *fname); +void report_hsp_secure_state(void); + #endif /* PSP_VERSTAGE_H */ diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 969c1c0863..33d92180c5 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -246,6 +246,9 @@ void Main(void) svc_write_postcode(POSTCODE_CONSOLE_INIT); console_init(); + if (CONFIG(PSP_INCLUDES_HSP)) + report_hsp_secure_state(); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); diff --git a/src/soc/amd/mendocino/psp_verstage/chipset.c b/src/soc/amd/mendocino/psp_verstage/chipset.c index fe79979fbe..c892b19e30 100644 --- a/src/soc/amd/mendocino/psp_verstage/chipset.c +++ b/src/soc/amd/mendocino/psp_verstage/chipset.c @@ -2,6 +2,8 @@ /* TODO: Check if this is still correct */ +#include <arch/hlt.h> +#include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> #include <cbfs.h> #include <console/console.h> @@ -113,3 +115,17 @@ void platform_report_mode(int developer_mode_enabled) else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); } + +void report_hsp_secure_state(void) +{ + uint32_t hsp_secure_state; + int ret; + + ret = svc_get_hsp_secure_state(&hsp_secure_state); + if (ret != BL_OK) { + printk(BIOS_ERR, "Error reading HSP Secure state: %d\n", ret); + hlt(); + } + + printk(BIOS_INFO, "HSP Secure state: %#8x\n", hsp_secure_state); +} |